1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a method of fabricating a semiconductor device capable of reducing parasitic capacitance between bit lines and a semiconductor device fabricated by the method.
2. Description of the Related Art
As semiconductor devices continue to become more highly integrated, horizontal intervals between metal interconnection lines formed on the same level must be reduced. However, if the intervals between the metal interconnection lines are reduced, crosstalk between the metal interconnection lines can occur, and parasitic capacitance between the adjacent metal interconnection lines electrically isolated by an insulating layer can increase. Therefore, problems can occur in that electrical signals of the semiconductor devices are erroneously transmitted and the transmission rate can decrease. The transmission rate of the signals transmitted through the metal connections is inversely proportional to delay constant RC. The dielectric constant of a metal interconnection insulating layer is one of factors affecting the delay constant. The lower the dielectric constant of the metal interconnection insulating layer, the lower the delay constant. Even in a case where the metal interconnection insulating layer is made of a low dielectric (low-k) material, the dielectric constant is still in a range of 2.5 to 3.5. In order to increase the signal transmission rate by decreasing the delay constant, the metal interconnection lines must be insulated by using a lower dielectric constant material. Therefore, among approaches for reducing the parasitic capacitance between the metal interconnection lines, there is proposed a method of forming voids made of air having a dielectric constant of about 1 in the metal interconnection insulating layer.
A method of forming voids between metal interconnection lines is disclosed in U.S. Pat. No. 6,303,464, entitled “Method and structure for reducing interconnection system capacitance through enclosed void in a dielectric layer” by Gaw, et al. In addition, another method is disclosed in U.S. Pat. No. 6,376,330, entitled “Dielectric having an air gap formed between closely spaced interconnect lines” by Fulford, Jr. et al.
Recently, as semiconductor devices such as DRAMs become more highly integrated, there is a need to implement a process for minimizing semiconductor chip sizes. According to the high integration of the semiconductor devices, the bit lines, which are one of components of the DRAM, are formed by using a fine processing technique. By shortening the intervals between the bit lines and reducing the sizes of the bit lines, the semiconductor devices can be scaled down. As the intervals between the bit lines are shortened, parasitic capacitance also occurs between the bit lines in a manner similar to the aforementioned metal interconnection lines.
In addition, since a plurality of bit lines are formed in a narrow space, the widths of the bit lines decrease, and the resistance increases due to a narrow cross-sectional area. The resistance and parasitic capacitance in the bit lines cause increase in a total resistance which blocks the flow of the electrical signals transmitted by circuits and causes signal transmission delay according to phase change. Since the signal transmission delay deteriorates the efficiency and performance of the semiconductor devices, the signal transmission delay must be prevented. Therefore, there is a need for a method of reducing the parasitic capacitance and resistance due to the bit lines. Among the methods of reducing the parasitic capacitance of the bit lines, there is proposed a method of decreasing the widths of the bit lines and increasing the intervals between the bit lines. However, since the sizes of the bit lines are closely related to the resistance, there is a limitation on the decrease in the size of the bit lines, and the increase in the sizes of the bit lines may be traded off with the tendency of reduction in the design rule. Therefore, there are proposed approaches for reducing the parasitic capacitance between the bit lines. The methods of reducing the parasitic capacitance between the metal interconnection lines disclosed in the aforementioned U.S. Pat. Nos. 6,303,464 and 6,376,330 have difficulty in being applied to general production methods for semiconductor devices such as DRAMs having a generally known capacitor-over-bit-line (COB) structure. A method of reducing the parasitic capacitance between the bit lines in a COB-structured DRAM device is disclosed in Korean Patent Publication No. 2004-0002234, titled “Method of forming bit lines in a semiconductor device” by Woo.
FIGS. 1A to 2B are cross-sectional views showing a method of fabricating a semiconductor device disclosed in Korean Patent Publication No. 2004-0002234. In FIGS. 1A to 2B, FIGS. 1A and 2A are cross-sectional view taken along a direction perpendicular to the bit lines, and FIGS. 1B and 2B are cross-sectional views taken along a direction parallel to the bit lines to cut a space between the bit lines.
Referring to FIGS. 1A and 1B, a lower interlayer insulating layer 21 having bit line contact holes are formed on a semiconductor substrate 1. The lower interlayer insulating layer 21 may be constructed with a silicon oxide layer. Next, a plurality of parallel bit line patterns 29 are formed to fill the bit line contact holes. In this case, the bit line patterns 29 may be formed by sequentially stacking the bit lines 25 and hard mask layer patterns 27. An upper interlayer insulating layer 33 having poor step coverage is formed on the semiconductor substrate 1 having the bit line patterns 29. As a result, voids 35 are formed between the bit line patterns 29. Since the voids are made of air, the voids have a very low dielectric constant of about 1.
Referring to FIGS. 2A and 2B, buried contact holes 37 are formed to pass through the upper interlayer insulating layer 33 and the lower interlayer insulating layer 21. In this case, the buried contact holes 37 and the voids 35 are opened to each other, so that air can pass between them. In this manner, if buried contact plugs are formed within the buried contact holes 37 opened to the voids 35 in a general subsequent process, the buried contact plugs can be formed within the voids. As a result, electrical short between the buried contact plugs can occur. Therefore, in order to prevent the buried contact holes 37 and the voids 35 from being opened to each other, general insulating spacers for covering side walls of the buried contact holes 37 may be formed.
However, as the semiconductor devices continue to become scaled down in size, the aspect ratios of the buried contact holes tend to increase. Therefore, in order to form the insulating spacers, in a case where conformal spacer insulating layers are formed on the entire surface of the semiconductor substrate having the buried contact holes 37, the spacer insulating layer is formed on inner walls of the voids 35, so that the voids 35 may become buried with the spacer insulating layer. Otherwise, the spacer insulating layer is formed with a predetermined thickness on the buried contact holes 37 and the inner walls of the voids 35, so that the buried contact holes 37 and the voids 35 may still be opened to each other.
In order to form the insulating spacers in a case where spacer insulating layers having poor step coverage on the entire surface of the semiconductor substrate having the buried contact holes 37, since the aspect ratio of the buried contact holes 37 is large, the spacer insulating layer is more rapidly formed on edge portions of upper regions of the buried contact holes 37. Therefore, the upper open region of the buried contact holes 37 may be covered with the spacer insulating layer, and the lower regions of the buried contact holes 37 may remain as empty spaces. As a result, it may be difficult to form the insulating spacers on the side walls of the buried contact holes 37 opened to the voids 35.
Accordingly, in the fabrication of the semiconductor devices such as COB-structured memory devices, using the general fabrication methods described above, it may substantially difficult to form the voids between the bit lines. Therefore, there is a need for new structures and methods for forming the voids between the bit lines.